1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and a manufacturing method for the same in which low voltage operation with low power consumption and high driving capacity is required. In particular, the present invention relates to a manufacturing method for a power management semiconductor device such as a voltage detector (hereinafter, referred to as VD), a voltage regulator (hereinafter, referred to as VR), or a switching regulator (hereinafter, referred to as SWR).
2. Description of the Related Art
A conventional technology is explained with reference to FIGS. 8A to 8C. FIGS. 8A to 8C are schematic cross-sectional views showing sequential process steps of a manufacturing method for a semiconductor device according to a conventional technology. An NMOS transistor having an offset type LDD structure is shown as an example.
AS shown in FIG. 8A, a P-type semiconductor substrate 141, for example, doped with boron at an impurity concentration to attain a resistivity of 20 Ωcm to 30 Ωcm, is subjected to, for example, ion implantation of boron at a dose of 1×1011 atoms/cm2 to 1×1013 atoms/cm2 and to annealing at 1,000° C. to 1,200° C. for several hours to ten-odd hours, to form a diffusion layer, or a P-type well 142. Then, a field insulating film 143, for example, a thermal oxide film with a thickness of several thousands Å to 1 μm, is formed on the substrate by a LOCOS method, and a part of the field insulating film 143 corresponding to a region for forming a MOS transistor is removed, to thereby form a gate insulating film 144, for example, a thermal oxide film with a thickness of 10 nm to 100 nm. The P-type semiconductor substrate 141 and P-type well 142 are subjected to ion plantation before or after the formation of the gate insulating film 144 to thereby control the impurity concentrations thereof.
Next, also in FIG. 8A, polycrystalline silicon is deposited on the gate insulating film 144, to which impurities are introduced through predeposition or ion implantation, and the polycrystalline silicon is subjected to patterning, to thereby obtain a polycrystalline silicon gate 145 which serves as a gate electrode.
Subsequently, for example, arsenic (As) ion is implanted at a dose of, preferably, 1×1014 to 1×1016atoms/cm2 so as to reduce a sheet resistance to form a high impurity concentration drain region 147 and a high impurity concentration source region 149 at a certain distance from the polycrystalline silicon gate 145. After that, for example, phosphorus ions are implanted at a dose of, preferably, 1×1012 to 1×1014atoms/cm2, to form a low impurity concentration drain region 148 and a low impurity concentration source region 150 in a self-alignment manner by using the polycrystalline silicon gate 145 as a mask.
Next, still in FIG. 8A, an interlayer insulating film 146 having a film thickness in the range of 200 nm to 800 nm is deposited.
Next, as shown in FIG. 8B, contact holes 154, 151 are formed for connecting wiring to each of the high impurity concentration source region 149 and the high impurity concentration drain region 147. Subsequently, metal wiring is formed through sputtering or the like and subjected to patterning; drain electrode metal 152 is connected to a surface of the high impurity concentration drain region 147 through the contact hole 150. (See, for example, Kazuo Maeda, “Semiconductor Process for Beginners” (Japanese), Kogyo Chosakai Publishing, Inc., Dec. 10, 2000, p. 30).
FIGS. 9A to 9E are schematic cross-sectional diagrams showing sequential process steps of a manufacturing method for a high-breakdown voltage semiconductor device according to another conventional technology. A part of the structure from a gate to a drain of a high voltage operating MOS transistor having a thick oxide film at a drain edge is shown as an example.
In FIG. 9A, a P-type semiconductor substrate 161, for example, doped by boron at an impurity concentration to attain a resistivity of 20 Ωcm to 30 Ωcm, is subjected to, for example, ion implantation of boron at a dose of 1×1011 atoms/cm2 to 1×1013 atoms/cm2 and to annealing at 1,000° C. to 1,200° C. for several hours to ten-odd hours, to form a diffusion layer, or a P-type well 162. Here, an explanation is given on process steps for forming a P-type well on a P-type semiconductor substrate, while a P-type well may also be formed on an N-type semiconductor substrate in a similar manner.
Then, a thick oxide film is formed on the substrate by a LOCOS method. Following the deposition and patterning of a silicon nitride film (not shown), impurities, for example, phosphorus ions are implanted at a dose of, preferably, 1×1011 to 1×1013 atoms/cm2, to form a thick oxide film, for example, with a thickness of 0.2 μm to 2 μm. Through these process steps, a low impurity concentration drain region 163 is formed below the thick oxide film 164.
Next, as shown in FIG. 9B, a thin oxide film is removed, followed by a formation of a gate insulating film 165.
Subsequently, as shown in FIG. 9C, polycrystalline silicon 167 is deposited, to which impurities are introduced through predeposition or ion implantation.
Then, as shown in FIG. 9D, the polycrystalline silicon 167 is subjected to patterning, to thereby obtain a polycrystalline silicon gate 168 which serves as a gate electrode.
Next, as shown in FIG. 9E, in order to form a high impurity concentration source region (not shown) and a high impurity concentration drain regions 170, for example, arsenic (As) ions are implanted at a dose of, preferably, 1×1014 to 1×1016 atoms/cm2 so as to reduce a sheet resistance.
According to the semiconductor device manufactured according to the conventional methods described above, formation of a drain region at a lower concentration of impurity for the purpose of ensuring high junction breakdown voltage, surface breakdown voltage, snap-back voltage, or a low impact ionization rate, results in a reduction in an ESD immunity, which may eventually lead to a case where the ESD immunity falls below standards. There also occurs a phenomenon in which a large amount of drain current causes a self-heating in the low impurity concentration region, particularly in a portion having a high resistance, causing a current concentration thereto, which leads to destruction of the element.
That is, inconsistency between important characteristics of a transistor and the ESD immunity sometimes comes out, and leads to a problem in that characteristics and standards cannot be satisfied together without increase in transistor size to face an increase in cost along with the increase in chip area.
Also, wiring metal in the contact region in general is not excellent in its coverage, which is about 20% of the wiring metal thickness in a flat area. Such low coverage is a main reason for limiting current density, which accordingly makes it difficult to pass a large amount of current without increase in a contact area.